Non-Volatile Memories (NVM) have a wide diffusion and have become very important for storing large amounts of data in many consumer-electronic products (such as computers, mobile phones, digital cameras, etc.) and in apparatuses of various types (e.g., electric household appliances, precision tools, and control units of vehicles).
In general, a NVM includes a plurality of memory cells each adapted to take a selected one between two states characterized by opposite characteristics (i.e., erased or programmed). In particular, in a NVM of the complementary type, the memory cells are organized in pairs, each including a direct memory cell and a complementary memory cell that define a location adapted to store an information bit (logic value 0 or 1). Each bit is stored by bringing the direct memory cell into a state corresponding to the bit (e.g., programmed for the logic value 0 and erased for the logic value 1), while the complementary memory cell is brought into a logic state corresponding to the complement of the bit.
Typically, the memory cells are organized in rows and columns to form a matrix structure. In addition, the matrix structure is subdivided into a plurality of sub-groups or sectors. The reading and writing operations on the cells of the memory are performed using ancillary components including row, column, and sector decoders, and logic circuits, which allow accessing the memory cells to perform the required operations. In particular, for limiting the complexity of a control system of the NVM often it happens that the operations are performed by acting simultaneously on a plurality of memory cells at the same time, for example, of a whole sector.
In the complementary NVM, a sector is in a written condition if all the locations store a bit (i.e., its memory cells are in different states), otherwise the sector is in a non-written condition (i.e., its memory cells are in the same state).
A reading operation of a sector occurs in a differential mode; for example, one or more sense amplifiers perform a comparison of electrical quantities (e.g., currents) provided by the two memory cells of each location for determining the stored bit according to their difference.
Conversely, a typical writing operation of a sector involves three distinct phases. A (first) soft-programming phase brings all the memory cells of the sector into the programmed state. A (second) erasing phase brings all the memory cells of the sector into the erased state. These two phases cause a substantially equal average number of operations on each memory cell, so as to ensure a substantially uniform ageing for all the memory cells. A (third) programming phase brings the memory cells of each location of the sector into the programmed or erased state corresponding to the bits to be written therein.
Each of the three phases just described has a respective time duration typically in the order of milliseconds (ms). Therefore, the total duration of the writing operation of the sector has a non-negligible duration, which may be problematic in applications in which a fast writing is required. Indeed, an excessive duration of the writing operation may lead to an inability to store the bits into the sector, or it may cause a partial writing thereof, events that may lead to malfunctions or efficiency degradations of a system in which the NVM is included.
For example, this problem has a particularly high impact in the case of writing of emergency data (e.g., instructions being currently executed in the system, registers of the performed processes and/or diagnostic information) as a result of a sudden interruption of electric energy (e.g., because of a shortcoming in the power grid or a battery depletion) or a critical malfunction, such as causing a system crash.